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Build ANVAYA with us

A clean-slate operating system for AI agents on RISC-V needs people from the ISA to the agent runtime: developers, hardware engineers, chip designers and fabs, researchers and writers. Tell us where you fit and we will find the right first step together.

Software developers

SW

Kernel and microkernel engineers, userland and runtime developers, tooling and CI authors. Rust-first nucleus, capability-first ABI, evidence-first releases.

RISC-V hardware developers

HW

Board bring-up, SoC integration, firmware and boot paths. Take the QEMU-proven nucleus to development boards and real cores.

RISC-V chip designers and fabs

SI

Silicon and IP designers, foundry and packaging partners. Shape the hardware primitives an AI-native, capability-secure OS wants from the ISA down.

Verification and security researchers

FV

Formal methods, model checking, proof engineering, adversarial review of capability semantics and the syscall surface.

Cryptographers

PQ

Post-quantum primitives, protocol design, key management for capabilities and attestation.

AI-systems and alignment researchers

AI

Agent execution semantics, oversight and audit trails, resource governance for autonomous workloads.

Docs, translation, community

DOC

Technical writing, RFC editing, translations, onboarding material and community stewardship.

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Company, lab, university or independent.

Areas of interest, relevant experience, hardware you have access to. At most two links.

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